1. Field of the Invention
The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to techniques for producing gate-level and structural descriptions used in a computer controlled EDA system for integrated circuit (IC) design.
2. Related Art
The rapid growth of the complexity of modem electronic circuits has forced electronic circuit designers to rely upon computer programs to assist and automate most steps of the circuit design process. Typical circuits today contain hundreds of thousands or millions of individual pieces or “cells.” Such a design is much too large for a circuit designer or even an engineering team of designers to manage effectively manually. To automate the circuit design and fabrication of integrated circuit devices, electronic design automation (EDA) systems have been developed.
An EDA system is a computer software system designers use for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this behavioral description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. The netlist description is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. The EDA system ultimately produces a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
FIG. 1 illustrates a portion of a typical design flow 10 for the design of integrated circuits (e.g., ASIC, microprocessors, microcontrollers, etc.). As shown, design flow 10 includes a simulation library 11, also known as the “golden” library or the “sign-off” library, which contains descriptions of the design cells, and upon which the downstream IC design is based. A significant amount of effort is expended into creating, verifying, refining and correcting the simulation library 11. The simulation library 11, containing a large number of cell descriptions written in a behavioral hardware description language (HDL), can only be read by behavioral simulation tools (e.g., Verilog simulator). Therefore, after the simulation library 11 is created designers create a separate test library 12 that mirrors the simulation library 11 to support rules checking and automatic test pattern generation (ATPG). Test library 12 typically includes ATPG models for use by ATPG tools 19.
One drawback of the prior art approach is that a manual re-coding process 15 must be performed by the designers to translate the simulation library 11 into the test library 12. For instance, simulation models of memories must be completely re-written into ATPG models. Significant “simulation-only” functionality must be identified and removed, while other “ATPG-only” functionality may need to be added. The manual re-coding process 15 is complicated and requires a high level of skill and knowledge in both behavioral modeling and ATPG modeling. Certain complex designs, such as content addressable memory (CAM), may be too overwhelming for manual re-coding process 15.
Another drawback of the prior art approach is that human error may be introduced in the manual re-coding process 15. Thus, an equivalence verification process 14 for verifying functional equivalence between the simulation models and the manually re-coded ATPG models is needed. Simulation models of the simulation library 11, however, can be simulated only by a behavioral HDL simulator (e.g., Verilog simulator), whereas the ATPG models in the test library 12 can be simulated only by ATPG tools. Therefore, the equivalence verification process 14 is a very complicated task.
Yet another drawback of the prior art approach is that, from a user's perspective, ATPG models are very different from behavioral models. Therefore, ATPG reports 20 generated by ATPG tools 19 may be unfamiliar to the users used to model 11. This makes the process of debugging ATPG models even more difficult.
Therefore, what is needed is a method and system for converting simulation models of memories into ATPG models without requiring a significant amount of re-coding. What is yet further needed is a method and system for minimizing verification between the simulation models and the ATPG models. What is yet further needed is a method and system for facilitating users in debugging errors of the ATPG models. In view of the above needs, the present invention provides a system and method for automatically generating ATPG models for memories from behavioral descriptions. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.